FPGA configuration time and PCIe secification

Hi JP,

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So my understanding is that this discussion is to meet the fpga configuration/pcie enumeration timing spec when the fpga card and the host pc use the same power source.

I am developing a card which is purely for learning purpose. So If I can power the fpga card separately and configure it well ahead of the pcie RST (i.e when PC enumerates) then i am good to go. Is that right ?

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If your board is a PCIe end-point (peripheral), then that end-point must be ready to handle PCIe enumeration bus cycles shortly after reset, otherwise the BIOS will not enumerate the board.

In some cases you can violate this requirement, and re-enumerate the PCIe bus at a later time. Linux supports this to some extent, but its a bit of a hack.

In your case, you can pretty much do whatever you like. Worst-case you hit reset on the PC and force a warm reboot.

Cheers,

Dave