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maybe You have the formula to calculate configuration time for EP4CGX22 by MAX II from a single quad SPI flash ( N25Q128A13ESE40G ) in PS mode with PFL inside MAX II.
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To start with, simply determine if you can configure the device fast enough, i.e., 7,600,040/80ms = 95MHz. If you were going to use a MAX II to generate the DCLK signal, you would ideally use a clock at twice this frequency, and generate the 95MHz square wave as a divide-by-2. The TimeQuest analysis document was written to analyze the timing requirements of that case.
You could conceivable clock the MAX II and DCLK from a common 95MHz signal, but you would have to then match the timing of the external 95MHz to the data generated by the MAX II. Its not impossible, but in my opinion, selecting a different device capable of using FPP mode is a much more reliably solution. I know, you might not have that option, I'm just providing my "process of elimination" for device selection and configuration.
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PFL user guide ( p. 50 ) has the formula only for FPP.
Or please tell what to modify in that formula so, that it can be used for PS instead of FPP.
Thank You again!
UPD.
Formula is needed for PS mode
with data compression.
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I'm not sure that any timing parameter provided for compression is reasonable. Is there documentation that shows the compression is linear with device density? i.e., that the bit-stream length for a half-full device is half as large as for a full device? If this documentation does not exist, then there is no way to predict that your configuration image is not going to "blow up", so that the configuration time exceeds the PCIe timing requirement.
Basically you have to decide why you have to use an EP4CGX22 for an application targeting PCIe.
Cheers,
Dave
Honored Contributor
