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Gauthier_Auvray's avatar
Gauthier_Auvray
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2 years ago

FPGA configuration FPP

Hello,

What happen if we configure a FPGA (CycloneIVGX) in FPP mode (RBF file written by microprocessor) with a file generated for the wrong package? Should we detect it by monitoring nSTATUS/CONF_DONE/INIT_DONE pins?

Thanks,

Gauthier

Configuration

9 Replies

  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,

    Thank you for reaching out. Allow me some time to look into your issue. I shall come back to you with findings.

    Thank you for your patience.

    Best Regards,

    Nazrul Naim


  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    To answer your question. Yes, to check whether the configuration is success or having some error can be detected by monitoring nSTATUS/CONF_DONE/INIT_DONE pins. For more information, if the FPGA is configured in FPP mode using a file generated for the wrong package, the possibility of the FPGA Fail to configure is high.


    Hope that answers your question.


    Best Regards,

    Nazrul Naim


    • Gauthier_Auvray's avatar
      Gauthier_Auvray
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      2 years ago

      Hello,

      Not sure to understand your answer.

      Do you mean that the FPGA will be configured with the file generated with the wrong package without reporting error on nSTATUS/CONF_DONE/INIT_DONE? (in that case the FPGA will will not be functionnal since pinout is different).

      Or do you mean that the FPGA is able to detect that the file does not match the FPGA package and will report it on nSTATUS/CONF_DONE/INIT_DONE pins?

      Thanks,

      Gauthier

  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    Sorry for the confusion. Yes the FPGA is able to detect that the file does not match the FPGA package and will report it on nSTATUS/CONF_DONE/INIT_DONE pins.


    Hope this answers your question.


    Best Regards,

    Nazrul Naim



  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Hello,
    the term "package" is ambiguous. Configuration files are specific for FPGA chips ( series, number of LEs). Same chip resides in different packages sharing the same JTAG ID and confunfiguration file.
    • Gauthier_Auvray's avatar
      Gauthier_Auvray
      Icon for New Contributor rankNew Contributor
      2 years ago

      Ok, sorry, let me precise:

      We have two versions of the same board with two different FPGAs (same serie, same number of LEs but different package

      1. One with FPGA EP4CGX150F31I7 (FBGA 896) with configuration file fpga_f31.rbf
      2. One with FPGA EP4CGX150F23I7 (FBGA 484) with configuration file fpga_f23.rbf

      What happens if we attempt to configure board 1 with fpga_f23.rbf?

      Thanks,

      Gauthier

  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,

    Technically you cannot use the same programming file across different packages as the pin's locations are different on each package.

    You may perform the migration across the devices within the same package type as you can see in the table below:

    Perhaps you may need to update the pin assignment in your design on a different package type.


    Hope that answers your question.

    Regards,

    Nazrul Naim


    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      2 years ago
      Hi,
      I believe the latest response doesn't answer the question. As far as I understand, you are asking about the same FPGA chip used in different packages. So "what happens"? The chip can't know which package it is mounted in, it will accept the configuration file although the pin mapping is possibly different. Effects may be different, including possible damage of FPGA or external hardware. You need to analyze the chip to package pin mapping to predict the effects. Unfortunately it's not directly specified for all FPGA series.
      It's probably possible to identify the external connection in your FPGA code, disable outputs and signal an error in case of misconfiguration.
  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,

    As we do not receive any response from you on the previous question/reply/answer that we have provided, for now I will set this case to Close-Pending.

    Regards,

    Nazrul Naim