Honored ContributorI have a code for in Altera project (Sensorless control algortihm) with resource utilization aroung 66000 gates. My supervisor wants me to do area optimization to reduce the gates. Can, any guide my how to do this.
Honored ContributorTools -> Advisors -> Resource Optimization Advisor
If you're trying to reduce basic logic, it's really hard. The big ones are: Memories/shift-registers that could go into RAM blocks but aren't DSP logic that isn't going into DSP blocks Usually when these things happen, it's pretty apparent. Decent sized RAMs going into logic take a ton of area and you'd know early on. DSP logic that doesn't use the DSP blocks usually fails timing and takes a ton of logic. So both of these are uncommon to begin with, and when they do happen are usually noticed right away unless the designers is just running code where they have no idea what's inside. After that, it's really hard to do anything noticable. The synthesis options(like synthesizing for Area) have a negligible option. The bottom line is synthesis does whatever is in the RTL, and removes anything not hooked up, duplicated, or unnecessary, and is quite good at that(too good, if you ask some). So your left with logic to do what your code is and that's it. Different synthesis algorithms can refactor to remove some LUTs here and there, but nothing specific. So changing options might reduce it a percent, maybe two. If you need a lot more, you really need to remove logic from the design or try to find some algorithmic trick to do it more efficiently. I've had users spend weeks flipping switches and what not because they were too big for their device, but eventually realize some logic had to go to the chopping block. It's really just a symptom of synthesis being efficient from the get-go.Honored ContributorHi,
1. First, determine your area optimization objectives. Ask how many gates have to be optimized. 2. Ask if you're allowed to get rid of some of the functionality in order to do optimizations. 3. Extract "Resource Utilization By Entity" section of the Fit report into a spreadsheet. That will allow you to easily see and analyze the utilization at the instance level. 4. Spend a lot of time analyzing the data from (3). Understand how much resources of different types (RAMs, DSPs, FFs) are available on that FPGA. 5. Identify modules with largest utilization that can be optimized and meet your goals from (1) 6. Compile the design with different area optimization options 7. Come up with different proposals that include actual area reduction numbers: - getting rid of some of the functionality - moving some of the logic between embedded RAMs, DSPs and FFs - rewriting RTL - area optimizations from (6) Thanks, Evgeni
