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Altera_Forum
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11 years ago

FPGA Area Optimization

I have a code for in Altera project (Sensorless control algortihm) with resource utilization aroung 66000 gates. My supervisor wants me to do area optimization to reduce the gates. Can, any guide my...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

1. First, determine your area optimization objectives. Ask how many gates have to be optimized.

2. Ask if you're allowed to get rid of some of the functionality in order to do optimizations.

3. Extract "Resource Utilization By Entity" section of the Fit report into a spreadsheet. That will allow you to easily see and analyze the utilization at the instance level.

4. Spend a lot of time analyzing the data from (3). Understand how much resources of different types (RAMs, DSPs, FFs) are available on that FPGA.

5. Identify modules with largest utilization that can be optimized and meet your goals from (1)

6. Compile the design with different area optimization options

7. Come up with different proposals that include actual area reduction numbers:

- getting rid of some of the functionality

- moving some of the logic between embedded RAMs, DSPs and FFs

- rewriting RTL

- area optimizations from (6)

Thanks,

Evgeni