FPGA Area Optimization

Tools -> Advisors -> Resource Optimization Advisor

If you're trying to reduce basic logic, it's really hard. The big ones are:

Memories/shift-registers that could go into RAM blocks but aren't

DSP logic that isn't going into DSP blocks

Usually when these things happen, it's pretty apparent. Decent sized RAMs going into logic take a ton of area and you'd know early on. DSP logic that doesn't use the DSP blocks usually fails timing and takes a ton of logic. So both of these are uncommon to begin with, and when they do happen are usually noticed right away unless the designers is just running code where they have no idea what's inside.

After that, it's really hard to do anything noticable. The synthesis options(like synthesizing for Area) have a negligible option. The bottom line is synthesis does whatever is in the RTL, and removes anything not hooked up, duplicated, or unnecessary, and is quite good at that(too good, if you ask some). So your left with logic to do what your code is and that's it. Different synthesis algorithms can refactor to remove some LUTs here and there, but nothing specific.

So changing options might reduce it a percent, maybe two. If you need a lot more, you really need to remove logic from the design or try to find some algorithmic trick to do it more efficiently. I've had users spend weeks flipping switches and what not because they were too big for their device, but eventually realize some logic had to go to the chopping block. It's really just a symptom of synthesis being efficient from the get-go.