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Altera_Forum's avatar
Altera_Forum
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21 years ago

FPADD FPMULT for NIOS + Cyclone

Hi,

Not completely tested and in AHDL for compactness (will make VHDL and Verilog versions later) but runs at around 100Mhz in C6 grade cyclone 3 stage latency

32 bit version adder is approx 470LE, mult is approx 750LE

Fully parameterisable - does double precision also (10bexp, 52bit mant + sign) - NOT IEEE as I designed it to be fast!

This should be all the parts needed (attached)....

Regards,

Steve.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Hi,

    Ok, Ok - here a front end so it handles IEEE - sheesh.

    Steve...
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Steve,

    Looks very interesting.

    Have you tested it as CI for NiosII ? If yes, could you share a reference design + peace of code showing the performance of your solution ?

    Thanks,

    Maga
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    --- Quote Start ---

    originally posted by maga@Aug 12 2004, 02:58 AM

    steve,

    looks very interesting.

    have you tested it as ci for niosii ? if yes, could you share a reference design + peace of code showing the performance of your solution ?

    thanks,

    maga

    --- Quote End ---

    Working on that right now - will post the full project when done - just handed out the FPcore as a general IP for some to play with...

    Steve ...