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Honored Contributor
Honored ContributorFPADD FPMULT for NIOS + Cyclone
Hi, Not completely tested and in AHDL for compactness (will make VHDL and Verilog versions later) but runs at around 100Mhz in C6 grade cyclone 3 stage latency 32 bit version adder is appr...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- originally posted by maga@Aug 12 2004, 02:58 AM steve,
looks very interesting.
have you tested it as ci for niosii ? if yes, could you share a reference design + peace of code showing the performance of your solution ?
thanks,
maga --- Quote End --- Working on that right now - will post the full project when done - just handed out the FPcore as a general IP for some to play with... Steve ...
