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Altera_Forum
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10 years ago

Floating point addition in vhdl

Hii

I want to add 4 floating point no.what will be the result range.I am using

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

this package.For example if I want to add two floating point no then the result range is

C= A+ B -- range of C is (max(A'right ,B'right)+1 downto min (A'left ,B'left))

and it is working fine .But when I am doing

C = A+B+D+E;

What will be the new C range.

If I am following the same as above I am getting an error

"D:/214ee1411/vhdl codes/floatarith/mul_1test/fmul_1.vhd" Line 50: Expression has 11 elements ; expected 9

Please help me with this.

Thank you

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Yes, now you've added brackets, it will only need 2 extra bits.

    But a+b+c+d will break down into: 

    
result := (((a+b) + c) + d);

    which does require 3 extra bits.

    --- Quote End ---

    I concur.

    But getting pedantic: each addition will generate an extra bit, so if n additions are concatenated (as you describe) the final addition delivers n additional bit. But the result only needs integer(ceil(log2(n))) extra bits so you can resize: 

    
signal    a, b, c, d : ufixed(HH downto LL) ;
constant NN : positive := 4;
signal    result : ufixed( HH + integer(ceil(log2(NN))) downto LL);
result := resize((((a+b) + c) + d),  HH + integer(ceil(log2(NN))), LL) ;