Floating point addition in vhdl

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Yes, now you've added brackets, it will only need 2 extra bits.

But a+b+c+d will break down into:

result := (((a+b) + c) + d);

which does require 3 extra bits.

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I concur.

But getting pedantic: each addition will generate an extra bit, so if n additions are concatenated (as you describe) the final addition delivers n additional bit. But the result only needs integer(ceil(log2(n))) extra bits so you can resize:

signal    a, b, c, d : ufixed(HH downto LL) ;
constant NN : positive := 4;
signal    result : ufixed( HH + integer(ceil(log2(NN))) downto LL);
result := resize((((a+b) + c) + d),  HH + integer(ceil(log2(NN))), LL) ;