Flex10k - LE optimization?

Use an lpm_counter configured for down mode (this ensures that fast carry chains are used, and the compare with zero comes for free).

-- Altera LPM components
library lpm;
use lpm.lpm_components.all;
...
    -- Bit counter
    bit_d <= to_slv(BIT_VALUE, BIT_WIDTH);
    u3: lpm_counter
        generic map (
            LPM_WIDTH     => BIT_WIDTH,
            LPM_DIRECTION => "DOWN"
        )
        port map (
            -- Simulation-only output (suppress Quartus II warning)
            --
            -- altera translate_off
            q      => bit_q,
            -- altera translate_on
            aclr   => rst,
            clock  => clk,
            sload  => bit_load,
            cnt_en => bit_en,
            cout   => bit_done,
            data   => bit_d
        );

Thanks Dave!

Actually, years (make that decades) ago when I was designing stuff with 74xx161 counters I'd use the carry-out as a load, so you'd 'shift' the range towards the end of the counter rather than the beginning. For example, rather than using a 10-bit counter and compare with 799, you'd use the carry to load the value to 1024-799, which shifts the range from 200-1023 and what is probably what I'll be using here as well.. Just means you've got to shift your sync / addressing around a bit :-)

Spent some time re-writing modules and managed to fit my entire design with 2% to spare :-) The VGA timing chain itself benefited greatly, saving 20 LE's just by switching over to lpm_counters up counters. The cout is great as it now serves as a load as well as an enable for the vertical timing. Note that you pay 1 LE for the additional cout and sload signal but despite that, it's all good!