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Altera_Forum's avatar
Altera_Forum
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13 years ago

Flex 6000

I understand that the Flex6000 series is a little outdated but its all I have to work with at the moment. I purchased the ByteBlasterMV and have both QuartusII 9.0sp2 and 12.0. What Im trying to do is read the configuration file that is already on the chip since Im not even sure which of the 10 chips have the right one. Thanks in advance.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    I began wondering if what Im doing is not possible. Or do I need to take the chips out of the board they are in and put them into some sort of config device. Any help is appreciated Ive been at this for days.

  • Altera_Forum's avatar
    Altera_Forum
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    How is the Flex6K configured?

    Via EPC1? If so, you can read back the PROM contents via JTAG. Unless it has been programmed with read protection.

    If you're using some other configuration scheme... then that will depend on the scheme.
  • Altera_Forum's avatar
    Altera_Forum
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    Forgive me since Ive never messed with these before. But I was under the impression I could use the ByteBlasterMV and read the config off the chip from the board that it was already on. Do I need a config device to be able to do this? Im just wanting to read the config and test it for functionality and which one has the right config.

  • Altera_Forum's avatar
    Altera_Forum
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    You can't read back the FPGA's configuration, it doesn't support it.

    What you probably can do is read back the configuration from the EEPROM.

    The FLEX6K is, like most other Altera FPGAs, volatile. Ie, when you power down the board it loses it's configuration.

    Somewhere on the board, you'll have a configuration EEPROM from which the FPGA's configuration is loaded on power up.

    There are two possible schemes to do that for an FLEX6K and the first step is to identify what kind of scheme your board is using.

    A common one is to use an EPC1 PROM, which can be read/written via JTAG. If you're using that, the EPC1 should show up in your JTAG chain.

    Another possible scheme, where you use a µP or CPLD to load the FPGA's configuration at power up.

    * JTAG => ByteBlasterMV
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks that cleared that up. I thought it was stored on chip not in EPROM. I did find the EPROM and its EPC1PC8. There is a JTAG connector for both chips and one for the EPROM labeled FPGA Download.