Flash memory not detected - Arria 10 Development kit

Hi,
user manual is suggesting this procedure to update flash memory through .pof

6.8.2. Programming the Flash Using Quartus Programmer

You can use the Quartus Programmer to program the flash with your Programmer Object File (.pof). Ensure the following conditions are met before you proceed:
• The Quartus Programmer and the USB-Blaster II driver are installed on the host computer.
• The micro-USB cable is connected to the FPGA development board.
• Power to the board is on, and no other applications that use the JTAG chain are running.
• The design running in the FPGA does not drive the FM bus.

Execute the steps below to program the Flash
1. Start the Quartus Programmer.
2. Click Auto Detect to display the devices in the JTAG chain.
3. Select the flash attached to the MAX V and then click Change File and select the path to the desired .pof. If the flash is not detected, configure the FPGA with \examples\board_test_system\image \\dummy.sof and then go to step 2, refer to Configuring the FPGA Using Programmer.
4. Turn on the Program/Configure option for the added file.
5. Click Start to program the selected file to the flash. Programming is complete when the progress bar reaches 100%.

I understand post #1 so that you are basically following the procedure, but attached flash doesn't show up with MAX V.
Possible reasons are:
- The MAX V isn't configured with the original design including PFL IP
- The loaded A10 design blocks flash memory bus, I guess that's the case e.g. with board update portal design. In this case the said dummy design should be loaded instead.

I'm assuming so far that user manual is correct and MAX V PFL has the described feature to show flash memory on autodetect.

It should be mentioned that flash programming through .pof and MAX V PFL is one of several options. I understand that the shipped examples are more focussing on using .flash files and board update portal. Therfore .pof option isn't described as detailed as it should.

The only explicite .pof programming files are in examples\board_test_system\image\PRD\cfi

If you load fpp_config.cdf, can access flash?

Hi,

Have you follow the userguide for this devkit? Are you able to program BTS?

Also, you can try below solution from our community case:

https://www.intel.com/content/www/us/en/docs/programmable/683269/current/programming-volatile-or-non-volatile.html

Regards,

Aiman

Apologize for the incorrect link. Please refer below for the community case:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Message-ID-18591-Error-Can-t-recognize-the-flash-device-that/td-p/642909

Regards,

Aiman

Hello FvM,

Thanks for your response. Yes I did try to follow the steps mentioned in the user guide and the switch configuration mentioned there.

There are couple of updates and questions from my end.

1) There was an option to add flash manually in the programmer, by clicking on the cpld (5M2210Z). I was able to add the CFI flash and it is showing up in the tool. image below. Is this also a correct way to add the flash?

2) Let's say I would like to go with pof option using the above step, will it still be fine? If yes, then which mode should I use to generate the pof?. where should I find that information?

3) Once I generate the pof with correct mode and configuration, should I program the CFI flash and then also the pag_0 and option_bits as shown below?

thanks for your time.

Hi,
the board uses 2x1Gbit flash memory, thus memory type should be specified as CFI_2gb.

User manual 6.8.1 shows the default flash memory map. I presume that PFL option bits and factory respectively user hardware (whatever you want to program) should use the defined settings to be recognized by the flash loader at boot time.

You may also check which settings are used in the default factory configuration, e.g. by decoding fpp_config.pof. Usually flash loader is reading option bits to determine where to find the FPGA configuration. Factory configuration DIP switch will be probably used to switch between factory and user configuration, but I'm not sure.

When I were you, I would expext clear instructions how to generate and flash .pof shipped with the board, also example .cof and .cdf files. I took only a brief tour around the support package, but apparently they are not there.

Hi,

I believe our team has response to your query through Intel Premier Support(IPS).

-the mode is passive parallel x32. The option start address and the .SOF start address should be set accordingly to the memory map, the .sof page should be 1.

-To program the .JIC file you have to use the JTAG mode. You can Auto detect the JTAG chain and than add the .JIC file to the Arria 10 device.

We will continue to provide our support through IPS for more information.

Regards,

Aiman