Forum Discussion
Honored Contributorfinal year project help needed in fir design
1. i m designing an fir filter actually what i m doing is representing the general fir equation in schematic logic using shift register in delay units, the multiplexer uses sel line common to both input signal and coefficients to select the data to be processed in the multiplier , the altera mega function wizard generates the pipemult function according to my requirements and xor for addition of the pipemult outputs .i can mail you the the file ...the problem is i cant understand how the different components are to be wired togather ..if any one can help .
2.secondly ther is another approach i m using in which i m generating vhdl coles for the fir euation behaviour but i need to add a package but as soon as i start analysis and synthesis it give an error top level design entity undefine ..but the thing is the entity name is add_std and the top level entity design name is also kept the same add_std so y is this occurint if u can please give me an example of pakage decleration6 Replies
Altera_ForumI completely agree, don't use std_logic_arith. Using numeric_std will keep you honest with signed and unsigned types. It sounds like you need to look through some basic vhdl if you don't know how to hook megafunctions together. Do some simple stuff with and adder or two and muxes that you build by hand and connect up. Megafunctions connect together in the same manner. http://esd.cs.ucr.edu/labs/tutorial/ has many examples you can synthesize and looks at from basic to a couple of moderately complex examples.
- Altera_Forum
can you also help me with my first problem how do know which connection line to use so that i can join different generated megafuction block files to create a complete connected design file
- Altera_Forum
thank you wat u mean to say is that i just declare the same package in the main program
- Altera_Forum--- Quote Start --- can't i do the analysis and sythesis of the package seperage ly of just saving the file add its up to work .all coz every time i compile the design it send top level entity no defined --- Quote End --- You cannot synthesise a package on its own because it contains no entities. You need a top level entity to synthesise. You might be best sticking the package into modelsim and compiling it there for syntax checking. Also, please use numeric_std instead of std_logic_arith.
- Altera_Forum
can't i do the analysis and sythesis of the package seperage ly of just saving the file add its up to work .all coz every time i compile the design it send top level entity no defined
- Altera_Forum
Hi
for 2 : ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; package example is ........... ........... end example ; --------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.example.all; entity filter is port( ..... ....
