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Honored Contributor
Honored Contributorfinal year project help needed in fir design
1. i m designing an fir filter actually what i m doing is representing the general fir equation in schematic logic using shift register in delay units, the multiplexer uses sel line common to bot...
Altera_ForumHonored Contributor
Honored ContributorHi
for 2 : ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; package example is ........... ........... end example ; --------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.example.all; entity filter is port( ..... ....
