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Altera_Forum's avatar
Altera_Forum
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16 years ago

final year project help needed in fir design

1. i m designing an fir filter actually what i m doing is representing the general fir equation in schematic logic using shift register in delay units, the multiplexer uses sel line common to bot...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I completely agree, don't use std_logic_arith. Using numeric_std will keep you honest with signed and unsigned types. It sounds like you need to look through some basic vhdl if you don't know how to hook megafunctions together. Do some simple stuff with and adder or two and muxes that you build by hand and connect up. Megafunctions connect together in the same manner. http://esd.cs.ucr.edu/labs/tutorial/ has many examples you can synthesize and looks at from basic to a couple of moderately complex examples.