FIFO issues

Thanks for the offer. Sorry if I'm including too much code here, but I thought I'd hand off the whole thing. The same thing happens if we use a DE2 board.

In order to make it easy to see what's happening we've wired it up to the switches and LEDs of the DE2 board using the standard QSF names. And sorry indenting is getting trashed in the cut-and-paste to here.

The relevant code for what buttons are going where follows:

--- Quote Start ---

assign data_in = {14'd0,SW[4:3]};

assign HEX00 = data_out[7:0];

.data(data_in),

.rdclk(KEY[0]),

.rdreq(KEY[2]),

.wrclk(KEY[3]),

.wrreq(KEY[1]),

--- Quote End ---

Mark

--- Quote Start ---

`define n0 8'b11000000

`define n1 8'b11111001

`define n2 8'b10100100

`define n3 8'b10110000

`define n4 8'b10011001

`define n5 8'b10010010

`define n6 8'b10000010

`define n7 8'b11111000

`define n8 8'b10000000

`define n9 8'b10010000

`define na 8'b10001000

`define nb 8'b10000011

`define nc 8'b11000110

`define nd 8'b10100001

`define ne 8'b10000110

`define nf 8'b10001110

module bin_2_hex(bin, hex);

input [3:0] bin;

output [7:0] hex;

assign hex = (bin == 4'h0) ? `n0:

(bin == 4'h1) ? `n1:

(bin == 4'h2) ? `n2:

(bin == 4'h3) ? `n3:

(bin == 4'h4) ? `n4:

(bin == 4'h5) ? `n5:

(bin == 4'h6) ? `n6:

(bin == 4'h7) ? `n7:

(bin == 4'h8) ? `n8:

(bin == 4'h9) ? `n9:

(bin == 4'ha) ? `na:

(bin == 4'hb) ? `nb:

(bin == 4'hc) ? `nc:

(bin == 4'hd) ? `nd:

(bin == 4'he) ? `ne: `nf;

endmodule

module FIFOtest(

CLOCK_50,

SW,

LEDG,

HEX0,

HEX1,

HEX2,

KEY

);

//master

input CLOCK_50;

input [17:0] SW;

output [8:0] LEDG;

output [7:0] HEX0,HEX1,HEX2;

input [3:0] KEY;

wire [15:0] data_in;

wire [15:0] data_out;

wire [3:0] size;

wire rd_wr;

wire [7:0] HEX00,HEX11,HEX22;

//wire enable;

assign data_in = {14'd0,SW[4:3]};

assign HEX00 = data_out[7:0];

bin_2_hex inst0(HEX00, HEX0);

bin_2_hex inst1(HEX11, HEX1);

bin_2_hex inst2(HEX22, HEX2);

FIFO16by16 write(

.data(data_in),

.rdclk(KEY[0]),

.rdreq(KEY[2]),

.wrclk(KEY[3]),

.wrreq(KEY[1]),

.q(data_out),

.rdempty(LEDG[1]),

.rdusedw(HEX11),

.wrfull(LEDG[0]),

.wrusedw(HEX22)

);

endmodule

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module FIFO16by16 (

data,

rdclk,

rdreq,

wrclk,

wrreq,

q,

rdempty,

rdusedw,

wrfull,

wrusedw);

input [15:0] data;

input rdclk;

input rdreq;

input wrclk;

input wrreq;

output [15:0] q;

output rdempty;

output [3:0] rdusedw;

output wrfull;

output [3:0] wrusedw;

wire sub_wire0;

wire [15:0] sub_wire1;

wire sub_wire2;

wire [3:0] sub_wire3;

wire [3:0] sub_wire4;

wire wrfull = sub_wire0;

wire [15:0] q = sub_wire1[15:0];

wire rdempty = sub_wire2;

wire [3:0] wrusedw = sub_wire3[3:0];

wire [3:0] rdusedw = sub_wire4[3:0];

dcfifo dcfifo_component (

.rdclk (rdclk),

.wrclk (wrclk),

.wrreq (wrreq),

.data (data),

.rdreq (rdreq),

.wrfull (sub_wire0),

.q (sub_wire1),

.rdempty (sub_wire2),

.wrusedw (sub_wire3),

.rdusedw (sub_wire4),

.aclr (),

.rdfull (),

.wrempty ());

defparam

dcfifo_component.intended_device_family = "Cyclone II",

dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",

dcfifo_component.lpm_numwords = 16,

dcfifo_component.lpm_showahead = "OFF",

dcfifo_component.lpm_type = "dcfifo",

dcfifo_component.lpm_width = 16,

dcfifo_component.lpm_widthu = 4,

dcfifo_component.overflow_checking = "ON",

dcfifo_component.rdsync_delaypipe = 5,

dcfifo_component.underflow_checking = "ON",

dcfifo_component.use_eab = "ON",

dcfifo_component.wrsync_delaypipe = 5;

endmodule

--- Quote End ---

--- Quote Start ---

wrclk and rdclk must be feeded by a real clock signal, and you must use the enable to control the read/write

--- Quote End ---

Thanks,

I'm not sure I understand what you are saying. Are you saying that for some reason the buttons on the board can't be used as a clock for the FIFO? We've had no problem before and we did encounter the same problem using a "real" wrclk though we've been using rdclk from a button the whole time. It seems to work fine other than dequeueing the last element.

As far as "enable to control the read/write" are you referring to the rdreq and wrreq lines or something else that we've managed to miss? Again I _think_ we are handling the rdreq and wrreq correctly (we have them be a "1" only on the clock edge we wish to read or write).

Sorry for all the questions, I'm just not sure what you're suggesting.

The problem with using anything other than a real clock for a clock is that you wont always have a proper clock, and you are very likely to violate setup and hold times.

The best solution - use a real clock for BOTH clocks and use the buttons as the read/write enable