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Altera_Forum
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15 years ago

FIFO issues

Hello all, I've been working on a project involving the Altera FIFOs and things seem to be largely well. We've encountered one significant problem however and have had no luck debugging it. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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wrclk and rdclk must be feeded by a real clock signal, and you must use the enable to control the read/write

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Thanks,

I'm not sure I understand what you are saying. Are you saying that for some reason the buttons on the board can't be used as a clock for the FIFO? We've had no problem before and we did encounter the same problem using a "real" wrclk though we've been using rdclk from a button the whole time. It seems to work fine other than dequeueing the last element.

As far as "enable to control the read/write" are you referring to the rdreq and wrreq lines or something else that we've managed to miss? Again I _think_ we are handling the rdreq and wrreq correctly (we have them be a "1" only on the clock edge we wish to read or write).

Sorry for all the questions, I'm just not sure what you're suggesting.