The fifo interface (http://www.ece.utexas.edu/~desimone/fifo_interface/) component interfaces a FIFO megafunction to the Avalon bus so the master can read or write it like a peripheral. It&#39;s pretty simple, really. This is one of those peripherals that makes no sense whatsoever for a normal microcontroller, because there are too many fundamental variables (how wide? how deep?). The main site (http://www.ece.utexas.edu/~desimone/fifo_interface/) has all the documentation, or if you don&#39;t believe in documentation, you could just go ahead and download the component (http://www.ece.utexas.edu/~desimone/fifo_interface/download.html). This component is released as free software under the GNU Lesser General Public License. Since it is something I&#39;m doing for fun, there is no guarantee of support. Of course, since it&#39;s open source, you&#39;re free to dive in and mess with your copy all you want. Feel free to identify bugs, suggest improvements, even send patches. There is a support topic on this forum, or you can try to contact me via email. Be advised that I&#39;m not constantly in my office, so email replies may take up to a day or two (or longer, if I&#39;m on travel). Have fun! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

Hello Mike, Thanks for your very useful contribution. I do however have a question which seems not to be answered by your documentation: I have created a read fifo (data towards nios) using your tool. On the processor port symbol appears a "clk_en_from_the_readFifo", in addition to the "fifo_rdreq_from_the_readFifo". I expect that the fifo_rdreq should go to the rdreq input in the fifo (external to nios) which I have generated using the megawizard, but whats the use of clk_en? On the symbol which I have got from the wizard I have no clk_en input. I browsed your documentation but could not find any mention of this pin. Can you give me a hint? thanks Hennnig Risoe national laboratory Denmark

--- Quote Start --- originally posted by larsen@Oct 12 2004, 08:51 AM i have created a read fifo (data towards nios) using your tool. on the processor port symbol appears a "clk_en_from_the_readfifo", in addition to the "fifo_rdreq_from_the_readfifo". --- Quote End --- That&#39;s a side-effect from something I don&#39;t quite understand about the undocumented Europa library. There&#39;s a vestigial "clk_en" output generated, which always drives a logic 1. It should be left unconnected. Removing it from the em_fifo.pl script would disable the internal read register. I&#39;m not sure why this is.

Thanks for your reply Mike. In the software part you have some pretty fancy macros. Would it be posible for you to post some code snippets on how they are intended to be used. Interrupt use would also be interesting to see. This would be realy helpfull for me as a new NIOS user. henning

--- Quote Start --- originally posted by larsen+oct 13 2004, 05:33 am--><div class='quotetop'>quote (larsen @ oct 13 2004, 05:33 am)</div> --- quote start --- in the software part you have some pretty fancy macros. would it be posible for you to post some code snippets on how they are intended to be used.[/b] --- quote end --- the register_bit macro is for use in that header only (to save me typing, clutter, and potential errors); it&#39;s# undef&#39;d on the way out. that said, the other macros defined are all named the standard altera way, e.g. iord_arlut_fifo_interface_regname(base) reads from a register, and iowr_arlut_fifo_interface_regname(base, value) writes to a register. for the bits in the status register, arlut_fifo_interface_status_bitname_ofst is the bit&#39;s offset, and arlut_fifo_interface_status_bitname_msk is the bit mask. for control register bits, change status to control. <!--quotebegin-larsen@Oct 13 2004, 05:33 AM interrupt use would also be interesting to see. --- Quote End --- I haven&#39;t written any interrupt-using code for a couple reasons:[list][*] My current application is so memory-constrained that I don&#39;t have interrupts (everything is polled), so I can&#39;t justify writing interrupt handler code I&#39;m not using, [*] Assumptions would need to be made that would likely not be valid (for example, I could write a HAL character-device driver, but that can&#39;t work when the FIFO width is greater than 8 bits without extraneous word splitting and merging), [*] The user will be able to write much better (read: more specialized to their application) code than I can, and [*] I&#39;m still learning SOPC Builder&#39;s and HAL&#39;s way of doing things. [/list]If you need a starting point for basic uses, I would recommend looking at the Altera Nios UART driver for a starting point. Anything I wrote would look a lot like that. If you want more specific help, please contact me by email.

Mike, Having done some fine-reading on the header file "arlut_fifo_interface_regs.h" and its macro&#39;s followed by a quick simulation I think I finally can contribute constructively to your fifo interface. The REGISTER_BIT macro should read #define REGISTER_BIT(regName, bitName, bitNum) ARLUT_FIFO_INTERFACE_##regName##_##bitName##_OFST = bitNum, ARLUT_FIFO_INTERFACE_##regName##_##bitName##_MSK = (1 << ARLUT_FIFO_INTERFACE_##regName##_##bitName##_OFST) The original one never takes account of the bitNum parameter (end of second line). regards henning

FIFO Interface | Altera Community

13 Replies

Altera_Forum
Honored Contributor
22 years ago
Thanks for your reply Mike.

In the software part you have some pretty fancy macros. Would it be posible for you to post some code snippets on how they are intended to be used.
Interrupt use would also be interesting to see.
This would be realy helpfull for me as a new NIOS user.

henning
Altera_Forum
Honored Contributor
22 years ago
--- Quote Start ---
originally posted by larsen@Oct 12 2004, 08:51 AM
i have created a read fifo (data towards nios) using your tool. on the processor port symbol appears a "clk_en_from_the_readfifo", in addition to the "fifo_rdreq_from_the_readfifo".
--- Quote End ---

That's a side-effect from something I don't quite understand about the undocumented Europa library. There's a vestigial "clk_en" output generated, which always drives a logic 1. It should be left unconnected.

Removing it from the em_fifo.pl script would disable the internal read register. I'm not sure why this is.
Altera_Forum
Honored Contributor
22 years ago
Hello Mike,

Thanks for your very useful contribution. I do however have a question which seems not to be answered by your documentation:

I have created a read fifo (data towards nios) using your tool. On the processor port symbol appears a "clk_en_from_the_readFifo", in addition to the "fifo_rdreq_from_the_readFifo".
I expect that the fifo_rdreq should go to the rdreq input in the fifo (external to nios) which I have generated using the megawizard, but whats the use of clk_en? On the symbol which I have got from the wizard I have no clk_en input.
I browsed your documentation but could not find any mention of this pin. Can you give me a hint?

thanks
Hennnig
Risoe national laboratory
Denmark

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FIFO Interface

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