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Altera_Forum
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21 years ago

FIFO Interface

The fifo interface (http://www.ece.utexas.edu/~desimone/fifo_interface/) component interfaces a FIFO megafunction to the Avalon bus so the master can read or write it like a peripheral. It's pre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hello Mike,

Thanks for your very useful contribution. I do however have a question which seems not to be answered by your documentation:

I have created a read fifo (data towards nios) using your tool. On the processor port symbol appears a "clk_en_from_the_readFifo", in addition to the "fifo_rdreq_from_the_readFifo".

I expect that the fifo_rdreq should go to the rdreq input in the fifo (external to nios) which I have generated using the megawizard, but whats the use of clk_en? On the symbol which I have got from the wizard I have no clk_en input.

I browsed your documentation but could not find any mention of this pin. Can you give me a hint?

thanks

Hennnig

Risoe national laboratory

Denmark