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Altera_Forum
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21 years ago

FIFO Interface

The fifo interface (http://www.ece.utexas.edu/~desimone/fifo_interface/) component interfaces a FIFO megafunction to the Avalon bus so the master can read or write it like a peripheral. It's pre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

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originally posted by larsen@Oct 12 2004, 08:51 AM

i have created a read fifo (data towards nios) using your tool. on the processor port symbol appears a "clk_en_from_the_readfifo", in addition to the "fifo_rdreq_from_the_readfifo".

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That's a side-effect from something I don't quite understand about the undocumented Europa library. There's a vestigial "clk_en" output generated, which always drives a logic 1. It should be left unconnected.

Removing it from the em_fifo.pl script would disable the internal read register. I'm not sure why this is.