Fastest 16bit parallel port (3.3V)

Hi Dorin,

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I am trying to build a kind of an All-Digital-PLL using a DDS from Analog Devices.

The DDS allows programming the output frequency by using a 8bit or 16bit parallel port,

which is sampled by a parallel clock generated by the DDS (PCLK max freq 250MHz).

I am looking for a FPGA/CPLD that is able to compute 3 additions and to provide the output to the parallel port using the 250MHz clock (or as fast as possible).

Can you recommend a device/ a device class?

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What is the Analog Devices part number? What FPGA part number?

Without knowing the DDS part number, it is impossible to know what logic standard the DDS interface uses. For example, LVDS would work fine, SSTL would work fine, but 3.3V LVCMOS would probably not. I think the fastest switching rate on that logic standard for the FPGAs is around 167MHz.

Cheers,

Dave

Thanks Dave,

the device is AD9910 and it uses a LVCMOS 3.3V interface.

If the 250MHz is not achievable,

I would settle for a device that can use the 250MHz Pclk

provided by the AD9910

and produce data at half clock rate (i.e. 125MHz).

Regards,

Dorin

Hi Dorin,

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The device is AD9910 and it uses a LVCMOS 3.3V interface.

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This looks pretty similar to the DDS in the AD9956.

Here's my notes on that component:

http://www.ovro.caltech.edu/~dwh/carma_board/ad9956_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/ad9956_tests.pdf)

The schematics and board layout can be downloaded and viewed here:

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

The DDS current-output will need to be filtered using an analog filter. In my application, the DDS output did not need to be higher than 50MHz. The filter design was simulated using LTSpice (its shown in the document I referenced).

I'd recommend buying an evaluation board for the part and testing it. It helps to find subtle part issues. For example, the CML output on the AD9956 does not have termination resistors internal to the part.

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If the 250MHz is not achievable,

I would settle for a device that can use the 250MHz Pclk

provided by the AD9910

and produce data at half clock rate (i.e. 125MHz).

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FvM indicates that 125MHz DDR to achieve the 250MHz is possible with LVCMOS signals.

You should create a design with the FPGA you plan to use, add appropriate pin capacitance to the FPGA-to-DDS connections, and then perform a TimeQuest timing analysis. That'll give you an idea of the timing margin.

What functionality are you trying to implement with the DDS?

Cheers,

Dave