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Altera_Forum
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14 years ago

Fastest 16bit parallel port (3.3V)

Hello everyone, I am trying to build a kind of an All-Digital-PLL using a DDS from Analog Devices. The DDS allows programming the output frequency by using a 8bit or 16bit parallel port, wh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I know that 250 MHz data rate (= 125 MHz output toggle rate) can be managed by recent FPGAs, also using the LVCMOS IO standard. Simultaneous switching noise is probably the most serious problem. The adder can be pipelined according to the available device speed, even by cutting a single add operation, if necessary.