Fastest 16bit parallel port (3.3V)

Hi Dorin,

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I am trying to build a kind of an All-Digital-PLL using a DDS from Analog Devices.

The DDS allows programming the output frequency by using a 8bit or 16bit parallel port,

which is sampled by a parallel clock generated by the DDS (PCLK max freq 250MHz).

I am looking for a FPGA/CPLD that is able to compute 3 additions and to provide the output to the parallel port using the 250MHz clock (or as fast as possible).

Can you recommend a device/ a device class?

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What is the Analog Devices part number? What FPGA part number?

Without knowing the DDS part number, it is impossible to know what logic standard the DDS interface uses. For example, LVDS would work fine, SSTL would work fine, but 3.3V LVCMOS would probably not. I think the fastest switching rate on that logic standard for the FPGAs is around 167MHz.

Cheers,

Dave