Faster: reg mem[] or M9K?

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Will use of M9K RAM blocks significantly speed up the design compared to storing data in regular registers (i.e. 'reg')?

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The huge mux chain involved with a register based memory array will considerably slow down the data access. Block RAM is faster in this situation.

RAM inference coding "style" reflects primarly hardware requirements. The first point to find out is if the intended design topology is implementable with block RAM or can be modified accordingly.

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The huge mux chain involved with a register based memory array will considerably slow down the data access. Block RAM is faster in this situation.

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Yes, this is exactly what i suspected but needed to have it confirmed before putting in work to convert my reg based mem array design to use block RAM.

Can you tell me what I need to do to make my verilog "compliant" with the QII requirements such that I can convert my mem[] based design to use M9K storage? Would use of a HDL template as the one shown below make this use M9K blocks?

// Quartus II Verilog Template
// Simple Dual Port RAM with separate read/write addresses and
// single read/write clock
module simple_dual_port_ram_single_clock
# (parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
	input  data,
	input  read_addr, write_addr,
	input we, clk,
	output reg  q
);
	// Declare the RAM variable
	reg  ram;
	always @ (posedge clk)
	begin
		// Write
		if (we)
			ram <= data;
		// Read (if read_addr == write_addr, return OLD data).	To return
		// NEW data, use = (blocking write) rather than <= (non-blocking write)
		// in the write assignment.	 NOTE: NEW data may require extra bypass
		// logic around the RAM.
		q <= ram;
	end
endmodule

Tricky, I can't pipeline my design further because the failing path shown by the TimeQuest screenshot is actually just to get the data out of the array and into the target register (i.e. reg [31:0] reg_rx_tlp_bus <= mem[index]; )

EDIT: I'm looking into using a Megawizard-generated "Simple Dual-port RAM" in my design. It should work fine since my memory actually need to write 64-bits but read 32-bits. I will have to do a fair bit of redesign and re-testing but it should be worth the work if it results in significantly better performance. Previously, I had to pipeline my design just to get the data out of my array-based memory in one cycle. I'm hoping to be able to gain one or two clocks of performance per read in the new design.

FYI: I ended up using a Megawizard-generated 2-port altsyncram module backed by M9K blocks. This works very well.

Thanks.