Faster frequency in PWM

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Instead of using unreasonable high clock frequencies, I suggest fractional PWM methods.

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Thank you for your help. How do I use fractional PWM methods.

I have this simple code in Verilog

duty_cycle [9:0] // 10 bits

duty_cycle = 50;

reg [31:0] counter = 0;

always @(posedg clk) begin

if (counter < 5000)

counter <= counter + 1;

else

counter <= 0;

pwm = duty_cycle >= counter;

end

Generate multiple clocks, shifted in phase by different amounts. This will reduce the operating frequency of any one clock whilst maintaining the high 'data' rate you require.

So, you need 200kHz * 5000 = 1GHz. Four PLL clocks at 250MHz, shifted by 90 degrees each, could be used to generate the PWM modulation you require. This will require a combinatorial final output stage whose timing will be tricky to analyse. If the absolute step size is critical this may be a problem.

The other way you could attack this is by using the transceivers present in Stratix parts. These will serialise data for you. They're (arguably) not intended to be use in such a way but that's not to say they can't be used in such a way. I'm not sure of the min/max operating frequencies the transceivers require but, in essence, this would allow you to operate at a greatly reduced clock frequency (e.g. 100MHz), present parallel data (e.g. 10-bit) and the hardware does the rest. Ensure you configure the transmitter to bypass the 8B/10B encoder.

Thanks a_x_h_75;

I already talked to my local Atlera FAE person. He suggested to use the same way transceivers that you mentioned about.

Best wish Xmas 2013.

Sean

Here's the basic idea of fractional PWM. The duty_cycle value is interpreted as n.m fixed point number. The integer part is compared with the pwm counter, m fractional bits are accumulated and overflow into the integer part. Please notice that the pwm method is also changed from natural to regular sampling.

wire  duty_cycle 
reg  duty_cycle_r; 
reg  counter = 0;
always @(posedg clk) begin
if (counter < 5000)
  counter <= counter + 1;
else
begin
  duty_cycle_r <= duty_cycle + duty_cycle_r; 
  counter <= 0;
end
pwm = duty_cycle_r >= counter;
end 

Using phase shifted clocks or Gigabit transceivers is of course an option. Before spending the effort, I would ask which degree of signal purity is actually required or meaningful at all for the application? A case where the ns jitter of a fractional pwm may matter is e.g. class D audio. But it's impact in the signal band can be still effectively eliminated by using higher order sigma-delta modulators instead of the simple first order integrator in the example.

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Here's the basic idea of fractional PWM. The duty_cycle value is interpreted as n.m fixed point number. The integer part is compared with the pwm counter, m fractional bits are accumulated and overflow into the integer part. Please notice that the pwm method is also changed from natural to regular sampling.

wire  duty_cycle 
reg  duty_cycle_r; 
reg  counter = 0;
always @(posedg clk) begin
if (counter < 5000)
  counter <= counter + 1;
else
begin
  duty_cycle_r <= duty_cycle + duty_cycle_r; 
  counter <= 0;
end
pwm = duty_cycle_r >= counter;
end 

Using phase shifted clocks or Gigabit transceivers is of course an option. Before spending the effort, I would ask which degree of signal purity is actually required or meaningful at all for the application? A case where the ns jitter of a fractional pwm may matter is e.g. class D audio. But it's impact in the signal band can be still effectively eliminated by using higher order sigma-delta modulators instead of the simple first order integrator in the example.

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Thanks FvM,

My application will be Synchronous Bck Converter DC-DC. I'm also looking for example in Verilog so I can implement the code into FPGA. I have inputs from SPI to FPGA are V_in, V_out, I_set, and L (maybe enable too). So FPGA needs to do PWM (PWM_high, PWM_low).

Do you know that Altera have example code that I can look at it?

Best,

Sean