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Altera_Forum's avatar
Altera_Forum
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12 years ago

Faster frequency in PWM

Hello all, I'm trying to get the fastest frequency of PWM output to GPIO on DE1 board. I max out PLL to 450Mhz clock for PWM of 5000 steps and only get 80 or 90 kHz output. 1. My goa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Instead of using unreasonable high clock frequencies, I suggest fractional PWM methods.

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Thank you for your help. How do I use fractional PWM methods.

I have this simple code in Verilog

duty_cycle [9:0] // 10 bits

duty_cycle = 50;

reg [31:0] counter = 0;

always @(posedg clk) begin

if (counter < 5000)

counter <= counter + 1;

else

counter <= 0;

pwm = duty_cycle >= counter;

end