Faster frequency in PWM

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Here's the basic idea of fractional PWM. The duty_cycle value is interpreted as n.m fixed point number. The integer part is compared with the pwm counter, m fractional bits are accumulated and overflow into the integer part. Please notice that the pwm method is also changed from natural to regular sampling.

wire  duty_cycle 
reg  duty_cycle_r; 
reg  counter = 0;
always @(posedg clk) begin
if (counter < 5000)
  counter <= counter + 1;
else
begin
  duty_cycle_r <= duty_cycle + duty_cycle_r; 
  counter <= 0;
end
pwm = duty_cycle_r >= counter;
end 

Using phase shifted clocks or Gigabit transceivers is of course an option. Before spending the effort, I would ask which degree of signal purity is actually required or meaningful at all for the application? A case where the ns jitter of a fractional pwm may matter is e.g. class D audio. But it's impact in the signal band can be still effectively eliminated by using higher order sigma-delta modulators instead of the simple first order integrator in the example.

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Thanks FvM,

My application will be Synchronous Bck Converter DC-DC. I'm also looking for example in Verilog so I can implement the code into FPGA. I have inputs from SPI to FPGA are V_in, V_out, I_set, and L (maybe enable too). So FPGA needs to do PWM (PWM_high, PWM_low).

Do you know that Altera have example code that I can look at it?

Best,

Sean