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Altera_Forum's avatar
Altera_Forum
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14 years ago

External Memory Interface Toolkit

Hello,

I'm trying to get the EMIF toolkit up and running and I'm having some difficulty with the CSR. Hopefully someone has run into this before and can help!

I can get to the point in system console where the interface is detected but I can't get the CSR to be recognized regardless of the configuration. According to the documentation, you just enable it under Controller Settings, set to Internal JTAG and it will appear when the device is scanned.

I'm getting a few warnings in Qsys that concern me. In particular, the CSR master reset has no synchronous edges but has an associated clock. The compilation report also shows warnings with the reset making me think that it's actually disabled. However, I don't see a way to connect it.

To add a few details, I'm running Quartus 11.0 and I'm using a DDR2 controller with UniPHY. I have a JTAG to Avalon Master Bridge connected through a clock crossing bridge to the avl port of the DDR2 controller. The calibration and margining reports show that everything is looking good but I'd like to gather as much data as I can.

Thanks for reading!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi,

    Did you ever resolve this problem? We are seeing similar behavior.

    Regards,

    Guy
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Unfortunately I'm still working on it. I put a Service Request in with Altera and I'm still trying to find the answer myself in parallel. If I find anything I'll be sure to post. If you get it working, I'd love to hear what you did to fix it.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Skaneta,

    Reading your post it's not clear if you have actually put together a DDR2 interface that works successfully on hardware. I am attempting to do this and I can't seem to even get past some basic things like calibration. I have been told DDR2 has not been tested on the Stratix V (only DDR3) . So, I'm curious if anyone, such as yourself, has actually implemented a DDR2 interface using the UniPhy/MegaWizard and have run it successfully on Stratix V hardware?

    Bruce...
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Bruce,

    I'm using a Stratix IV GX so I'm not sure it's useful to you. However it is DDR2 with UniPhy and it has been successfully tested in hardware using the Memory Test example in SBT for Eclipse and a few parts of the EMIF toolkit. I've been working through calibration in another thread if you're interested. The only piece I'm missing now is the CSR so I can use the full functionality of the EMIF toolkit.

    http://www.alteraforum.com/forum/showthread.php?t=32337

    Hope this helps,

    Scott