errors occur when I use ddr controller IP

Hi,

everybody.

I use DDR IP in my design.

first, I create a new project and set a blank .bdf as top entity. Then, I use plug_in manager create a DDR control.

In my .bdf file, I import the PLL and the DDR controller symbol. then compile the project.

but , quartus 9 give the following errors:

//====================================================

Error: Post compile timing analysis failed (retcode=1)

Info: The most likely cause of this type of error is:

Info: (1) Some signals on the local-side interface are not connected causing logic to be optimised away,

Info: This script requires that the complete logic for the specified width of the datapath (both read and write paths) be present in the design.

Info: (2) The clear-text HDL files for the datapath may have been modified.

Info: (3) Not all clocks from the system pll are global.

Error: Output clocks to SDRAM Not Found

Error: Output clocks to SDRAM Not Found

Error: In-System timing verification of DDR/DDR2-SDRAM Megacore variation 'DDRip' could not be completed due to the above errors.

Error: Evaluation of Tcl script auto_verify_ddr_timing.tcl unsuccessful

Error: Quartus II Shell was unsuccessful. 5 errors, 0 warnings

Error: Peak virtual memory: 55 megabytes

Error: Processing ended: Thu Jun 10 10:43:46 2010

Error: Elapsed time: 00:00:03

Error: Total CPU time (on all processors): 00:00:02

Error: Quartus II Full Compilation was unsuccessful. 7 errors, 121 warnings