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kleaviat's avatar
kleaviat
Icon for New Contributor rankNew Contributor
1 year ago

Error(18210): LogicLock region assignments cannot be used in Quartus Prime Pro Edition. Remove these

Dear,

I am currently building an FPGA design in Quartus Pro II ver. 16.0.0, because initial design and its IP cores were created in mentioned version. When we run "FITTER" function of the compilation I get following error.

Error(18210): LogicLock region assignments cannot be used in Quartus Prime Pro Edition. Remove these assignments, or modify them to use LogicLock Plus region assignments.

Based on the web (https://community.intel.com/t5/Intel-Quartus-Prime-Software/LogicLock-Arria10-issues-with-Platform-Designer-projects/m-p/1352489) I assume that I have an issue in the syntax of constrained files. The open ticket mentions that problem is in a wild card "*". I have tried to use proposed solution but it didn't help (exp. set_false_path -from [get_registers {*|*sd2~cs_css/dclk_bump.reg}] -to [get_ports NCSO*])

Is there another way to solve the problem which I have?

Thank you very much for your help

Best,

Kleaviat

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3 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    No, the issue is just what the error says. The format of Logic Lock .qsf assignments changed in Pro at some point IIRC ("Logic Lock Plus"), so just like the error says, you should delete and then recreate your LL assignments using the Logic Lock assignments window and/or Chip Planner.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

    If you have any further questions or concerns, please don't hesitate to let us know.

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    Richard Tan