Forum Discussion
kleaviat
New Contributor
New ContributorError(18210): LogicLock region assignments cannot be used in Quartus Prime Pro Edition. Remove these
Dear, I am currently building an FPGA design in Quartus Pro II ver. 16.0.0, because initial design and its IP cores were created in mentioned version. When we run "FITTER" function of the compilatio...
RichardT_altera
Super Contributor
Super ContributorYes, as the error message stated, you will need to remove all Logic Lock assignments in your QSF file.
You may also visit this webpage to check the cause of Quartus error messages and the respective actions to resolve them.
Regards,
Richard Tan
