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Altera_Forum
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14 years ago

Error with Ethernet Design

I followed the instruction from the course "10/100/1000 Mb Ethernet Design with Altera Transceiver Devices: Introduction (OTSE1116)", and I got this error: 

Error: System.altera_ethernet_1: altera_ethernet_1.receive and eth_mon_inst_1.avalon_streaming_sink must be on the same clock domain, since they're connected.

Can anyone tell me how to fix it? :D

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Yeah, I changed the clock and that worked. Now I got these errors: 

    Error: The design contains 2 blocks of type "Embedded multiplier block" but the selected device EP4CGX15BF14C8 does not support such blocks
	Info: Node name: tse_ref_design:tse_ref_design_inst|tse_ref_design_cpu:cpu|tse_ref_design_cpu_mult_cell:the_tse_ref_design_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_gkr2:auto_generated|ded_mult_e091:ded_mult1|mac_mult2. Implement the design block using soft logic by choosing the relevant option in the related megafunction
	Info: Node name: tse_ref_design:tse_ref_design_inst|tse_ref_design_cpu:cpu|tse_ref_design_cpu_mult_cell:the_tse_ref_design_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ikr2:auto_generated|ded_mult_e091:ded_mult1|mac_mult2. Implement the design block using soft logic by choosing the relevant option in the related megafunction
Error: The design contains 2 blocks of type "Embedded multiplier output" but the selected device EP4CGX15BF14C8 does not support such blocks
	Info: Node name: tse_ref_design:tse_ref_design_inst|tse_ref_design_cpu:cpu|tse_ref_design_cpu_mult_cell:the_tse_ref_design_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_gkr2:auto_generated|ded_mult_e091:ded_mult1|mac_out3. Implement the design block using soft logic by choosing the relevant option in the related megafunction
	Info: Node name: tse_ref_design:tse_ref_design_inst|tse_ref_design_cpu:cpu|tse_ref_design_cpu_mult_cell:the_tse_ref_design_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ikr2:auto_generated|ded_mult_e091:ded_mult1|mac_out3. Implement the design block using soft logic by choosing the relevant option in the related megafunction

    I guess the original project made for Stratix IV, but I changed the device setting to Cyclone IV in Qsys and Quartus. I am not sure if it is the reason for these errors, and I don't know how to fix. :D
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Recreate the project from begining only using this project as reference.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    open up the Nios in Qsys and change the Hardware multiplication type to Logic Elements or None

    the smallest CIVGX doesn't have hardware multiplier blocks for some reason
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I changed the Hardware multiplication type to Logic Elements, and I got this error: 

    Error: Selected device has 60 RAM location(s) of type M9K.  However, the current design needs more than 60 to successfully fit
	Info: List of RAM cells constrained to M9K locations
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_en"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_err"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet:altera_ethernet|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_en"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_err"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"
		Info: Node "tse_ref_design:tse_ref_design_inst|tse_ref_design_altera_ethernet_1:altera_ethernet_1|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_mac_pcs_pma_strx_gx_ena:altera_tse_mac_pcs_pma_strx_gx_ena_inst|altera_tse_top_1000_base_x_strx_gx:top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_tx_converter:U_TXCV|pcs_data"

    :D
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Seems like it's too small for the multipliers to be embedded in memory blocks :)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    i don't think the two problems are related, you've moved past the multiplier problem to an on chip RAM problem. you can see the hierarchy path is different

    i don't know a lot about the TSE Ethernet core, but i would open it up and try and decrease the buffer sizes to use less on chip RAM

    as you can see, the CIVGX15 is a very small device