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Altera_Forum
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16 years ago

Error: Peak virtual memory: 255 megabytes

Hello,

I'm new to FPGA. I'm doing this for a 4th year course and I'm facing a problem.

When I compile the project, I'm getting these errors: 


Error: Design contains 10582 blocks of type logic cell.  However, device contains only 10570.
Error: Can't fit design in device
Error: Quartus II Fitter was unsuccessful. 2 errors, 526 warnings
	Error: Peak virtual memory: 255 megabytes
	Error: Processing ended: Wed Nov 04 22:13:32 2009
	Error: Elapsed time: 00:22:22

I went through the "Resource Optimization Advisor" but no luck (I'm not sure If I'm not supposed to do this).

Please help me with this issue. I literally spent the whole day trying to solve it.

Regards,

Khalid

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Your design is using too many logic resources. If you post it here, we may be able to help optimize it.

    What device family are you using?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Your design is using too many logic resources. If you post it here, we may be able to help optimize it.

    What device family are you using?

    Jake

    --- Quote End ---

    Hello Jake,

    Thanks for your reply. It's NIOSII Stratix 1S10.

    I'm following a tutorial by Altera. http://www.altera.com/literature/tt/tt_nios2_multiprocessor_tutorial.pdf (page 33)

    Which part do you want me to copy? It's a design in SOPC Builder. It was generated there successfully, but when I compiled it in Quartus I got this error.

    Just so you know, I could compile it at the university lab but I can't using my laptop. I don't think it's a matter of a computer resources, right?

    Thanks in advance.

    Khalid
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    No it's not a computer resource issue. The design you are creating is actually too large to fit in the Stratix device.

    Since you mentioned doing it at home rather than at school, I wonder if the reason it compiled at school is that your university actually has a license for the IP cores you are using. If you don't have a license (which I assume you don't on your laptop), the design actually uses more logic because it inserts some logic to support the OpenCore Plus evaluation of the core. This logic is used to make the IP timeout after an hour of running on the FPGA.

    Regardless, just zip the whole project folder and post it. If that is too large, you can archive the project from within Quartus and just post the archive here.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    BTW, at school we have the full licensed 8.0 and the web edition 9.0. And we're using the web edition (same as the one I have in my laptop).

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hmmm. Not sure what the problem is but when I try to open the project, Quartus crashes on me. I'll see if I can work around it.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Well, it compiled for me (I ended up using 9.1). It's extremely full (10,467 LEs out of 10,570). Now I should note that just because you are using the web edition at school doesn't mean they don't have a valid IP license. If this exact same project compiles on my machine, and your machine a school, but not your laptop; I can think of no other reason than you don't have the same IP licenses (for things like NIOS processor) that you have at school.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Pleaaaaaaaaaaaaaaaase :(

    I'm counting on you...

    --- Quote End ---

    Hi,

    I have a good and a bad message for you. The good one I could run your project , but it doesn't fit. I will have a brief look to it.

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Hi,

    I have a good and a bad message for you. The good one I could run your project , but it doesn't fit. I will have a brief look to it.

    Kind regards

    GPK

    --- Quote End ---

    Hi,

    the bad news is that your design needs 12302 logic elements. I got this number by running

    your design with a larger device selected. The number of the logic elements you got with the error message is not correct ( I never trust this numbers in the past). Your device has only 10xxx logic elements. I'm pretty sure that you will not get a fit without modifying ( means reduce your design size) your design. Even the best area optimization algorithm will not bring down your design to the required size. Sorry for this bad news.

    Kind regards

    GPK