Honored Contributor
Honored ContributorNo it's not a computer resource issue. The design you are creating is actually too large to fit in the Stratix device.
Since you mentioned doing it at home rather than at school, I wonder if the reason it compiled at school is that your university actually has a license for the IP cores you are using. If you don't have a license (which I assume you don't on your laptop), the design actually uses more logic because it inserts some logic to support the OpenCore Plus evaluation of the core. This logic is used to make the IP timeout after an hour of running on the FPGA. Regardless, just zip the whole project folder and post it. If that is too large, you can archive the project from within Quartus and just post the archive here. Jake
