Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Error: Peak virtual memory: 255 megabytes

Hello,

I'm new to FPGA. I'm doing this for a 4th year course and I'm facing a problem.

When I compile the project, I'm getting these errors:


Error: Design contains 10582 blocks of type logic cell.  However, device contains only 10570.
Error: Can't fit design in device
Error: Quartus II Fitter was unsuccessful. 2 errors, 526 warnings
	Error: Peak virtual memory: 255 megabytes
	Error: Processing ended: Wed Nov 04 22:13:32 2009
	Error: Elapsed time: 00:22:22

I went through the "Resource Optimization Advisor" but no luck (I'm not sure If I'm not supposed to do this).

Please help me with this issue. I literally spent the whole day trying to solve it.

Regards,

Khalid

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Well, it compiled for me (I ended up using 9.1). It's extremely full (10,467 LEs out of 10,570). Now I should note that just because you are using the web edition at school doesn't mean they don't have a valid IP license. If this exact same project compiles on my machine, and your machine a school, but not your laptop; I can think of no other reason than you don't have the same IP licenses (for things like NIOS processor) that you have at school.

    Jake

    --- Quote End ---

    Hi Jake,

    did you something special or is it only the new Quartus Version ? I treid the same with Quartus 9.0 and it didn't fit.

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I didn't do anything special. For some reason I can't open the project in 9.0 without Quartus crashing. Please do something for me:

    1 - Open the compilation report for your project.

    2 - Expand the "Analysis & Synthesis" section of the report.

    3 - Click on the "IP Cores Summary" report.

    This will give you a list of the IP used in the project along with it's corresponding license. If any of those IP cores have an OpenCore evaluation license, your design will consume more logic when you build it than when I build it.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    I didn't do anything special. For some reason I can't open the project in 9.0 without Quartus crashing. Please do something for me:

    1 - Open the compilation report for your project.

    2 - Expand the "Analysis & Synthesis" section of the report.

    3 - Click on the "IP Cores Summary" report.

    This will give you a list of the IP used in the project along with it's corresponding license. If any of those IP cores have an OpenCore evaluation license, your design will consume more logic when you build it than when I build it.

    Jake

    --- Quote End ---

    Hi Jake,

    thanks for your info. I did not get the "IP Cores Summary", but the warning during Analysis & Synthesis that the NIOS II will use the Evaluation feature. I never get the

    information that the synthesis results of an evaluation version will be worse than the

    licenced version.

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Your design is using too many logic resources. If you post it here, we may be able to help optimize it.

    What device family are you using?

    Jake

    --- Quote End ---

    Hi

    I get the same problem now, but the strange thing is my project once compiled before. I'm using a Cyclone 3c25 board and used a 60kb on-chip memory to accomodate 'fopen' and 'fclose' commands. I once tested my project and it did compile. Now it doesnt anymore. I heard that it could have to do with the license or something? Could it be the problem?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I've got this problem. There's a VHDL syntax error warned before in my code.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I was trying something like this in quartus 13.0 SP1 CycloneII device.

    cmplxAdd add2(.z(addOut2),.x(inp1), .y({-inp2[63:32],-inp2[31:0]});

    And received Error: Peak virtual memory: 462 megabytes.

    I changed the above instantiation as

    cmplxAdd add2(addOut2, inp1, {-inp2[63:32],-inp2[31:0]});

    and the error vanished.

    Whats the difference in the above two statements which is causing the Peak Virtual Memory error?

    Or is this a bug in Quartus ?