Error (10686) Aggregate value

Hi,

I am trying to use a reduction operator on a wire to check for zero. I used to do this all the time using model sim, but now it seems there is some problem with using any reduction operator.

The offending block:

// control logic block
always @ ( Ctrl, A, B ) begin
	case (Ctrl)
		// arithmetic operations
		3'o0, 3'o1, 3'o4: begin
			Z = ~|Ath_out ;	// high if zero <- Error!!!
			V = V_ath ;	// set to Arith_16b overflow output
			N = Ath_out  ; // MSB is sign bit
		end
		// logical operations
		3'o2, 3'o3: begin
			Z = ~|Log_out ;	// high if zero <- Error!!!
			V = 1'b0 ;		// reset
			N = 1'b0 ;		// reset
		end
		// shifts do not change flags
		default: begin
			Z = Z ;
			V = V ;
			N = N ;
		end
	endcase
end

The error in the analysis stage this produces is:

Error (10686): SystemVerilog error at ALU_16b.v(99): Ath_out has an aggregate value

Error (10686): SystemVerilog error at ALU_16b.v(105): Log_out has an aggregate value

Ath_out (Log_out) is the output of a submodule defined here:

/

/ module outputs
wire Ath_out  ;	// arithmetic output
wire V_ath ;						// overflow flag from arith module
wire Log_out  ;	// logical output
wire Sft_out  ;	// shift output

and BITWIDTH is a parameter defined by:

parameter BITWIDTH = 16 ;

I am pretty clueless about what the problem is. I've tried not using the parameter and just hard coding the bitwidth in but the same error occurs. Any help would be greatly appreciated.