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Altera_Forum's avatar
Altera_Forum
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14 years ago

Error (10686) Aggregate value

Hi, I am trying to use a reduction operator on a wire to check for zero. I used to do this all the time using model sim, but now it seems there is some problem with using any reduction operato...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Well the problem was that i was defining my vectors as unpacked arrays 

wire Ath_out  ;    // arithmetic output

needs to be: 

wire  Ath_out ;    // arithmetic output

Apparently the former will compile in system verilog. Hopefully someone else learns from this. :cry:

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Thanks very much - this helped me a lot. I knew about the packed form, but forgot it and got this error. Thanks!