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Altera_Forum's avatar
Altera_Forum
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14 years ago

error 10482

I'm writing my vhdl code for a lab assignment. When I try to simulate, I get this error and don't understand what it means: Error (10482): VHDL error at LW6.vhd(15): object "down" is used but not declared

port( DHC : in bit_vector(2 down to 0);

LEG7: out bit_vector(6 down to 0);

RSEG7: out bit_vector(6 down to 0);

I, J, A, B, SONIC : out bit );

end entity LW6;

Any help appreciated,

Steve

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    bit_vector(2 down to 0);

    --- Quote End ---

    Review your VHDL text book or a Altera Quartus example. You should write downto not down to.