Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

error 10170: HDL syntax error in Verilog

Hi, i got some trouble for the code i developed: when i execute this code: if(rst==1'b1) begin 38. cs [0] = 4'b0; 39. cs [1] = 4'b0; 40. cs [2] = 4'b0; 41. cs [3] = 4'b0; 42. cs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

it quite easy, you shoud declare "module shifter16(A,H_sel,H);" not "module shifter16 (A, H_sel, H)"

to complete a command line include module declareation, you must use ";"

:)