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Altera_Forum
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12 years ago

error 10170: HDL syntax error in Verilog

Hi, i got some trouble for the code i developed: when i execute this code: if(rst==1'b1) begin 38. cs [0] = 4'b0; 39. cs [1] = 4'b0; 40. cs [2] = 4'b0; 41. cs [3] = 4'b0; 42. cs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi,

Using 2014 version of Quartus II software (web edition), I have problem compiling the following code receiving error 10170. 

module shifter16 (A, H_sel, H)
    input A;
    input H_sel;
    output H;
    reg  H;
    always @ (A or H_sel)
    begin
        if (H_sel)
            H={A,1'b0};
        else
            H={A,A};
    end
endmodule

Error received:

Error (10170): Verilog HDL syntax error at shifter16.v(2) near text "input"; expecting ";"

Any help would be appreciated.