Forum Discussion
AdzimZM_Altera
Regular Contributor
18 days agoHi SUHAS_KRISHNA,
I would suggest to check the DDR component with the EMIF Example Design.
You may refer to user guide to generate the example design from the link: https://docs.altera.com/r/docs/683842/21.1/external-memory-interfaces-arria-10-fpga-ip-design-example-user-guide/generating-the-synthesizable-emif-design-example
Please enable the EMIF Debug Toolkit as following instruction to check the calibration details of the DDR: https://docs.altera.com/r/docs/683106/current/configuring-your-emif-ip-for-use-with-the-debug-toolkit
Regards,
Adzim