EPCS16 in AS Mode

Your EPCS could be broken. See also a recent thead: http://www.alteraforum.com/forum/showthread.php?t=23988

Did you try a verify after programming? If that's ok, there's another cause.

Good luck, Ton

--- Quote Start ---

hello, I have the same problem, the JTAG working properly but when I configure the EPCS16 nothing happens, I followed all the steps described in the DE2 manual, also I performed the "verify" and everything goes right in the console. I am using the version 9.1 of Quartus. Someone found the solution?

--- Quote End ---

unselect the generate compressed bitstreams field in your device configuration

hi all,

well i am also having same problems in the same domain of working of EPCS16, well i was able to program the device, by the same configuration mention in the handbook, but the problem is that when i turn on my system, it wont load the code form EPCS16, is there any change i have to make again like to MSEL bits??

also the system works fine when i program via JTAG.

so what could be the reason, if any one has the clue please do let know

Regards

Unfortunately I meet the same problem. I use EPCS16 with EP3C25F324I7. I can download sof file with JTAG and everything is OK.

I also can download pof file with AS, and verified, but the system doesn't work after reboot.

the "generate compressed bitstreams" field is unselected.

--- Quote Start ---

Unfortunately I meet the same problem. I use EPCS16 with EP3C25F324I7. I can download sof file with JTAG and everything is OK.

I also can download pof file with AS, and verified, but the system doesn't work after reboot.

the "generate compressed bitstreams" field is unselected.

--- Quote End ---

well, to this i would first suggest to check the interconnection between EPCS and FPGA. i.e. is the ckt upto the standards of Altera, it would be nice if you could add the ckt diagram. many of the times it happens so that there is something not correct and so after bootup FPGA gets false configuration. Also how are you managing the MSEL but lines, during and after configuration?? i mean with a micro-controller or with a Jumper??

Thanks for thepancake's opinion, I will try it right now.

And thank ammar as well.

The interconnection between EPCS and FPGA are according to the handbook. The same schem works when I connect a EPCS4 with EP3C16Q240(Only the pin definition are different from EP3C25F324) in another board, so I don't think there are problems.

MSEL[3:0] is constantly 0010.

Maybe I should check the dclk timing, because I am using a 50M crystal which may be a little high.

I will post my results later.

--- Quote Start ---

Maybe I should check the dclk timing, because I am using a 50M crystal which may be a little high.

--- Quote End ---

As long as you don't supply a userclock, dclk will be always generated by the FPGA internally, it hasn't to do with the FPGA input clock frequency.

Signal integrity of DCLK may be a problem though, particularly if the distance between FPGA and AS EPCS16 is long. There have been reports about need for a serial dclk termination even with short distance: http://www.alteraforum.com/forum/showthread.php?t=26422

Thanks.

Yes, It has nothing to do with the external crystal as DCLK is supplied by internal 10M clock.

The problem is exactly the same as described in the thread http://www.alteraforum.com/forum/showthread.php?t=26422 (http://www.alteraforum.com/forum/showthread.php?t=26422)

Configuration is correct when I touch a scope probe on the DCLK.

I have tried to connect a 1K resister or a 47nF capacitor between DCLK and GND, but it didn't contribute.

I will look for other means to solve the problem instead of replacing the EPCS16 with EPCS4.

I have tried to Disable AS mode CONF_DONE error check, but it doesn't matter.