--- Quote Start ---
Maybe I should check the dclk timing, because I am using a 50M crystal which may be a little high.
--- Quote End ---
As long as you don't supply a userclock, dclk will be always generated by the FPGA internally, it hasn't to do with the FPGA input clock frequency.
Signal integrity of DCLK may be a problem though, particularly if the distance between FPGA and AS EPCS16 is long. There have been reports about need for a serial dclk termination even with short distance:
http://www.alteraforum.com/forum/showthread.php?t=26422