Forum Discussion
Altera_Forum
Honored Contributor
16 years agoEPCS16 in AS Mode
hi, i cannot configure the EPCS16 in AS Mode with my appplication, i have downloaded the xxx.pof file with succes in my device but by reseting i can't see some effect i don't know where the ...
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- Maybe I should check the dclk timing, because I am using a 50M crystal which may be a little high. --- Quote End --- As long as you don't supply a userclock, dclk will be always generated by the FPGA internally, it hasn't to do with the FPGA input clock frequency. Signal integrity of DCLK may be a problem though, particularly if the distance between FPGA and AS EPCS16 is long. There have been reports about need for a serial dclk termination even with short distance: http://www.alteraforum.com/forum/showthread.php?t=26422