epcs controller

You could also use the ALT_REMOTE megafunction directly.

The .pdf from it is good, and easy to understand.

I used it together with a small (20 lines) state machine, and it gets the job done.

The c4up.v is generated using altera megacore wizard. The rcu.v is an implementation similar to the cyc3 of sopc builder because altera didn't release the source.

So it is the core for sopc builder. You can look at the driver code of cyc3 and do it in a similar way.

Beside, if there is still a chance touch the hardware, you would be better to use PS mode to configure the fpga (no need the epcs and remote update as AS mode).

- Hippo

Yes, it is true but I intended to use REMOTE UPDATE inside SOPC.

This is Your verilog program but I would to use ALTERA standard block.

I read that after CYCLONE III there are possibilities to program multioot system inside EPCS.

I read some PDF but at the moment is not so clear for me and I needed some example.

Bye

G

The page I mentioned is a remote update core which you can access with spi avalon master bridge.

- Hippo

Hi Hippo,

1. I can't implement NIOS II because I havent space inside FPGA

2. When I spoke about REMOTE UPDATE I intended REMOTE UPDATE block inside SOPC. It is an ALTERA BLOCK and I would to use it.

Bye

G

Please check an example at

http://nioswiki.com/exampledesigns/remote_update/remote_update_for_cyclone_iv_e

The fpga will start with factory configuration, you will need to program remote update core to load user configuration next.

Another suggest, you might add a nios2 core and use spi slave. This will make your fpga a smart peripheral.

MPU SPI Master -> fpga[ spi slave -> nios2 -> onchip mem, rcu, spi flash etc. ]

- Hippo

I changed my design . I'm using MPU SPI to connect SPI AVALON MASTER BRIDGE to configure and read/write FPGA adn the same SPI to program EPCS.

I removed EPCS controller that insime my project is not important.

At hte momento I have this problem: because when HOST MPU is programming EPCS there are a possibility that EPCS should be wrong written, after this operation my board doesn't start more.

So I need to implement REMOTE UPDATE : I'm using CYCLONE IV and this is possible.

Somebody has some example ? I'm reading altera's datasheet but is not so clear and I would try a simple.

Bye

G

hippo seams to have a nice solution.

The one I use assumes that your MPU does not have a SPI port.

Don't call it epcs. It is just a spi flash, you can find data and app note from stmicro.

The method to convert sof to binary data for epcs/spi flash programming is replied in another post from you.

Though your original plan is possible, it is extremely complex and slow. I would suggest another approach, control the spi flash directly. You may instant asmiblock primitive from quartus/libraries/megafunctions, which is just io pins to spi flash.

MPU SPI master -> FPGA[ --> pass through-> asmi ] -> spi flash.

wire MISO,MOSI,SCLK,SS_n;

asmiblock the_tornado_epcs_controller_atom

(

.data0out (MISO),

.dclkin (SCLK),

.oe (1'b0),

.scein (SS_n),

.sdoin (MOSI)

);

Hi Amilcar,

do You have an example for ALTASMI_PARALLEL?

I noted that there isn't ALTASMI_PARALLEL inside SOPC object, so I don't know how can I connect it to my SOPC block.

Bye

G