epcs controller

Why don't you use ALTASMI_PARALLEL ?

It works great.

even the HAL does not tell everything about the epcs controller, normaly you would think okay that epcs device is an SPI memoy so lets have a look at the possible manufacture datesheets to lern more about it.

but there is something between this spi functionality and the epcs related pins specially that you cannot add a simple custom spi functionality. it seems to be possible now with cyclone III, but i haven't tryed that

Hi Amilcar, can You send me an axample with ASMI?

My problem is: I have to write EPCSand my microcontroller HOST is connecte with FPGA ALTERA with SPI to avalon master bridge.

I have to write EPCS. Do You have an example?

For MSchmitt: thanks but I haven't to program EPCS directly with SPI HOST. I have HOST connected with FPGA and FPGA have to write EPCS.

Bye

G

Hi Ferraro,

EPCS is like a regular SPI flash of STmicro. EPCS controller is a Altera SPI controller and a hidden onchip memory.

So your configuration might look like this,

MPU ->FPGA[ bridge -> avalon MM bus ->Altera SPI master-> ] EPCS

Right?

- Hippo

Hi Hippo,

my configuration is different. I have:1

MPU HOST (as SPI master) connected with FPGA (here SPI as slave: spi_slave_to_avalon_mm_master_bridge). FPGA is connected as ACTIVE SERIAL and I have to program EPCS with HOST MPU.

This is my problem. Hardware is done and I haven't other possibilities.

For this reason I would to know how EPCS CONTROLLER run and control word bit's meaning.

In my idea I HAVE TO REALIZE (HOST SOFTWARE):

1. use SOF2FLASH to convert .sof into .flash (S-record)

2. write .flash inside HOST flash (by remote control)

3. software to convert .flash to SPI PHYSICAL LAYER for spi_slave_to_avalon_mm_master_bridge with commands for EPCS CONTROLLER

Can You tell me something about point 3?

I have some difficult to find correct use of EPC CONTROLLER.

Bye

Hi Amilcar,

do You have an example for ALTASMI_PARALLEL?

I noted that there isn't ALTASMI_PARALLEL inside SOPC object, so I don't know how can I connect it to my SOPC block.

Bye

G

Don't call it epcs. It is just a spi flash, you can find data and app note from stmicro.

The method to convert sof to binary data for epcs/spi flash programming is replied in another post from you.

Though your original plan is possible, it is extremely complex and slow. I would suggest another approach, control the spi flash directly. You may instant asmiblock primitive from quartus/libraries/megafunctions, which is just io pins to spi flash.

MPU SPI master -> FPGA[ --> pass through-> asmi ] -> spi flash.

wire MISO,MOSI,SCLK,SS_n;

asmiblock the_tornado_epcs_controller_atom

(

.data0out (MISO),

.dclkin (SCLK),

.oe (1'b0),

.scein (SS_n),

.sdoin (MOSI)

);

hippo seams to have a nice solution.

The one I use assumes that your MPU does not have a SPI port.

I changed my design . I'm using MPU SPI to connect SPI AVALON MASTER BRIDGE to configure and read/write FPGA adn the same SPI to program EPCS.

I removed EPCS controller that insime my project is not important.

At hte momento I have this problem: because when HOST MPU is programming EPCS there are a possibility that EPCS should be wrong written, after this operation my board doesn't start more.

So I need to implement REMOTE UPDATE : I'm using CYCLONE IV and this is possible.

Somebody has some example ? I'm reading altera's datasheet but is not so clear and I would try a simple.

Bye

G

Please check an example at

http://nioswiki.com/exampledesigns/remote_update/remote_update_for_cyclone_iv_e

The fpga will start with factory configuration, you will need to program remote update core to load user configuration next.

Another suggest, you might add a nios2 core and use spi slave. This will make your fpga a smart peripheral.

MPU SPI Master -> fpga[ spi slave -> nios2 -> onchip mem, rcu, spi flash etc. ]

- Hippo