EPC16 does not configure EP2C35 at high temperature

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What does the timing of dclk and data0 look like at the fpga?

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During a bad cycle, the DCLK and DATA0 are dead - flatlined.

During a good config cycle - they look reasonable enough. I will try to capture a waveform and post it. The CycloneII and EPC device are only a couple of inches apart.

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Could it be a problem in the soldering process?

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I have seen this on multiple boards. I have not seen any specific issue with the soldering process on any other device on these boards.

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According to the waveforms, the EPC16 is simply not starting configuration after nSTATUS is deasserted. So I guess, the problem is related to this device rather than the FPGA. The reason for configuration failure can't be explained from the shown waveforms, I think. But it may be probably caused by other EPS16 signals, e. g. an incorrect terminated TCK.

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After the nSTATUS is de-asserted, wouldn't you expect the FPGA to take over and start toggling the DCLK. Once it receives the first frame of data, it will pulldown the INIT_DONE signal.

Good thought about the TCK - I will check.

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wouldn't you expect the FPGA to take over and start toggling the DCLK

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In PS mode, DCLK is controlled by the configuration device. But it's apparently never starting configuration, although all prerequisites are met according to the waveform.

Another question: What happens, if you start a configuration manually through EPC16 JTAG interface?

You might also check your power and grounding setup.

Or decoupling?

These will be harder to detect with scope shots, but may be why the EPC sometimes fails at elevated temps?

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In PS mode, DCLK is controlled by the configuration device. But it's apparently never starting configuration, although all prerequisites are met according to the waveform.

Another question: What happens, if you start a configuration manually through EPC16 JTAG interface?

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Yes the EPC16 definitely looks like the culprit here.

The device programs fine via JTAG.

I collected some waveforms.

Here is the power up sequence - The VCCINT is up and stable 100ms after VCCIO comes up.

http://i43.tinypic.com/iei5h2.jpg

This is a zoomed out view of the good config cycle. It takes about 442ms after power for the configuration to be complete and for the CONF_DONE pin to go high.

http://i39.tinypic.com/2d85hyw.jpg

These waveforms show DCLK and DATA0 - these signals have ~2V pk-to-pk ripple on the waveforms.

http://i41.tinypic.com/2yla4r6.jpg

However, we did find something interesting.

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Another question: What happens, if you start a configuration manually through EPC16 JTAG interface?

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Once the device does not get configured at power up (BAD CONFIG cycle), I cannot successfully program the device over JTAG. I can Auto-Detect the part - but when I try to load a file, it returns - can't recognize silicon id for device 2.

My JTAG chain looks like this

BYTE_BLASTER_HEADER --> FPGA --> EPC16

I can configure the FPGA just fine. So the TDI/TDO & TCK connections are OK. But I just cannot configure the EPC device.

However, once the device does gets configured at power up (GOOD CONFIG cycle - by freezing the EPC16), I can successfully program the device over JTAG. It does not matter if the board has been on for a while and the device is not "cold"; I can still program the EPC.

This indicates that - during power up, when it is hot, the device falls into a "bad state". This causes it to fail configuration and not respond to JTAG either. Any idea what could cause this device to go into a dead or idle state at power up?

I have checked TCK/TMS/TDI/TDO during steady state - they seem OK. I have not looked at these during power up yet.

This does feel like one step forward in some direction - not sure where.

Any ideas are much appreciated.