Forum Discussion
Altera_Forum
Honored Contributor
17 years agoI collected some waveforms.
Here is the power up sequence - The VCCINT is up and stable 100ms after VCCIO comes up. http://i43.tinypic.com/iei5h2.jpg This is a zoomed out view of the good config cycle. It takes about 442ms after power for the configuration to be complete and for the CONF_DONE pin to go high. http://i39.tinypic.com/2d85hyw.jpg These waveforms show DCLK and DATA0 - these signals have ~2V pk-to-pk ripple on the waveforms. http://i41.tinypic.com/2yla4r6.jpg However, we did find something interesting. --- Quote Start --- Another question: What happens, if you start a configuration manually through EPC16 JTAG interface? --- Quote End --- Once the device does not get configured at power up (BAD CONFIG cycle), I cannot successfully program the device over JTAG. I can Auto-Detect the part - but when I try to load a file, it returns - can't recognize silicon id for device 2. My JTAG chain looks like this BYTE_BLASTER_HEADER --> FPGA --> EPC16 I can configure the FPGA just fine. So the TDI/TDO & TCK connections are OK. But I just cannot configure the EPC device. However, once the device does gets configured at power up (GOOD CONFIG cycle - by freezing the EPC16), I can successfully program the device over JTAG. It does not matter if the board has been on for a while and the device is not "cold"; I can still program the EPC. This indicates that - during power up, when it is hot, the device falls into a "bad state". This causes it to fail configuration and not respond to JTAG either. Any idea what could cause this device to go into a dead or idle state at power up? I have checked TCK/TMS/TDI/TDO during steady state - they seem OK. I have not looked at these during power up yet. This does feel like one step forward in some direction - not sure where. Any ideas are much appreciated.