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Altera_Forum's avatar
Altera_Forum
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19 years ago

"end of initialization" reset

Hi everybody, Are there internal power-up reset or "end of initialization" reset signals that can be read to check for start-up reset condition in cyclone FPGA's? Whitebird
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Thank you for fast answer Brad.

The problem with INIT_DONE is that I don't know id it can be read internally

--- Quote Start ---

Every internal register will be cleared at power up

--- Quote End ---

OK, but it seems not to be the case for state machines.

I have a state machine like that (VHDL):

type state_machine is(P1,P2,P3);

signal state,statef:state_machine;

But after end of initialization the first state is P2 and not P1! I want it to be P1.

Don't know why it goes to P1.

The state will be P1 only by the help of an external reset pin.

Whitebird