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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Enabling HPS JTAG on DK-DEV-AGI027RBES

Hi,

The HPS JTAG signals of the Agilex7 device on the DK-DEV-AGI027RBES are directly connected to the MAX10 device. They have been properly setup within Quartus following the IO assignment provided in the DK-DEV-AGI027RBES schematics. The HPS is able to boot the FSBL using u-boot, confirmed by the UART output. However, DS-5 cannot connect to the A53_0, or any of the A53s, with the error:

Unable to connect to A53_0.

Reason:
The target hardware identity could not be verified. Please check that the target being connected to is of type Agilex SoC

Is there any special consideration that needs to be taken in order to connect the On-board Intel FPGA Download Cable II to the HPS JTAG chain?

Thank you,

Ricardo.

Generic Io

12 Replies

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Ricardo


    This you select the arm A53 under the Intel SoC FPGA during the target selection?


    Intel SoC FPGA > Agilex > Bare Metal Debug > Debug Cortex-A53_0


    Regards

    Jingyang, Teh


    • RicardoC's avatar
      RicardoC
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Jingyang,

      Thank you for the response. This is how it is configured:

      It is a bit different that what you mentioned. Does it look OK?

      Thank you,

      Ricardo

    • RicardoC's avatar
      RicardoC
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi @JingyangTeh_Altera,

      Do you have an update on how to configure the DK-DEV-AGI027RBES so that the HPS_JTAG signals of the Agilex part are in the JTAG chain?

      Thank you,

      Ricardo.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Ricardo

    Sorry for the late response.

    Apparently this issue is a known problem and there are efforts to get this resolved.

    It is expected to have a detailed instruction on a new programming file for the MAX10 within the next two weeks.

    Regards

    Jingyang, Teh

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Ricardo


    I believe that your FAE have contacted and shared with you the changes needed to by your FAE.


    I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


    Regards

    Jingyang, Teh


  • RicardoC's avatar
    RicardoC
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi Jingyang,

    The released document does not discuss about the inclusion of the HPS CPU JTAG into the board JTAG chain. Was it addressed in the new MAX10 image?

    Thank you,

    Ricardo

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Ricardo


    It is a new image for the MAX10 device that will bridge the HPS JTAG to the JTAG chain.

    In the documentation there are instruction on flashing the new MAX10 image and you see the HPS JTAG on the jtag chain.


    Regards

    Jingyang, Teh


    • RicardoC's avatar
      RicardoC
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Jingyang,

      I have not been able to test it because the reference design used in the released document makes use of an Ethernet controller, a Nios V and some other 3 IPs that we don't have license for.

      I will update this thread when I'm able to try it.

      Thank you,

      Ricardo.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Ricardo


    Any update on this case?

    If you got problem with the licensing, you could try getting a evaluation license first while the process of acquiring a license is going on.


    Regards

    Jingyang, Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


    Regards

    Jingyang, Teh